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Chip Design Optimization Techniques
Nov 07, 2017

Chip design optimization techniques

1) The rise of mobile applications, the importance of power consumption gradually appear. Large power consumption means shorter battery life.

2) The improvement of chip integration makes power supply system design a challenge.

As technology advances, the density of circuits within a chip multiplies exponentially, and operates at frequencies several times higher than before, while the on-chip connections are getting thinner and the on-chip power supply network must power more power with less power Line resources are sent to each cell, and if this is not possible, the stability of the chip and the intended operating frequency will all become issues. IR voltage drops and the amount of cabling resources consumed by the power supply network are important issues plaguing backend designers, and this pressure is now being transmitted step by step to the front-end designers, requiring less power needed during the design phase.

3) The impact of power consumption on cost is increasingly significant

Power consumption determines the chip's heat, the package structure in time to transfer the heat generated by the chip to go, or the temperature rise, resulting in the circuit can not be stable. Therefore, the heat-generating chips need to choose a good heat dissipation package, or additional cooling system, such as fans, which means the cost increases.

For these reasons, power consumption has become an important indicator of products and constraints. The following factors in the design of the beginning, it should be included in the designer's consideration:

  1) Determination of power consumption target

A) the commercial value of power consumption in the application area of the product;

B) cost of package and process;

C) the feasibility and complexity of the implementation, and the resulting assessment of design risks and schedule implications;

D) The selection of reference value: According to similar products, experience, tool analysis to determine, and with the deepening of the design constantly revised.

  2) optimization program (strategy) settings

Before going further analysis, let's look at the composition of power consumption.

2 power consumption of the composition

  2.1 core power

Power consumption consists of RAM, ROM, clock tree (clock tree) and the core logic (Core logic) in four parts, the following analysis.

1) RAM

The calculation of RAM power consumption is a complex task. Fortunately, the memory compiler can do this for us. The rate at which the key points are accessing each port can be obtained by considering the access pattern type or by simulation. It is suggested to generate the RAM / ROM power consumption data of different parameters (width, depth, speed, port number) in the early stage of design to facilitate the design exploration.

2) Clock tree

The power consumption of the clock tree accounts for 40% ~ 60% of the power consumption of the entire chip because of its high activity rate (100%) and power consumption both positive and negative edges.

Among them, the capacitor contains register capacitance, drive unit capacitance and connection capacitance of three parts.

3) core logic circuit

Define the core logic circuit power consumption in addition to the combination of the clock tree and the timing unit power consumption. Consists of two parts:

Leakage current and capacitive loads

4) macro cell 

Most chips include analog macros such as PLLs, which can be found from the library vendor's data sheet. Designers can cut down on unworked modules by slicing the system mode to reduce power consumption.

  2.2 IO power

IO power consumption includes IO unit, external load, external terminal and so on. Because of the need to drive board-level wiring, the capacitance of IOs can be hundreds of times larger than the internal cells, thus consuming more power. Occasionally IO power consumption can account for a large percentage of overall power consumption, and system architecture may change due to: redefinition of system partitioning to reduce chip-to-chip connectivity; choice of different IO interface protocols to reduce energy consumption. IO power consumption is usually determined by the system architecture, interface bandwidth, and protocol requirements. Once the library is selected, the designer can optimize the space is small, but the core power consumption is reduced by designers, in the following pages, we will be the core power estimation and optimization as the theme.

3 power estimation

The value of power estimation is to see the optimization results quantitatively as early as possible to help designers explore the initial architecture. At each stage, such as product planning, architectural development, code writing, synthesis, P & R, designers are faced with several options to immediately see the results of the choice, rather than the end of the design process, can effectively reduce development time.

4 power optimization

4.1 The principle of optimization

Our goal is to reduce the clock tree, standard cell and memory power consumption. Power consumption and performance are often full of contradictions:

1) make the clock slower (less conversion), but we want faster processing speed.

2) Reduce Vdd, but smaller Vdd limits the clock speed.

3) Less circuitry, but more transistors can do more work.

In short, we want to accomplish the maximum amount of tasks with the least amount of energy. The way to achieve this is to fine-tune the control of the circuit's movements, allowing only the circuits that are just needed to operate within the required time without wasting any effort. To accomplish this task, designers need to manage the circuit's actions efficiently.

Modern systems are so complex that designers have to cut them down into layers and step by step to grasp:

Software -> Architecture -> Logic -> Circuits

In each level, designers have different control over the range and means of circuit operation. Software is the master dispatcher for hardware actions, and the designer can turn off the entire module or reduce invalid actions depending on the particular application. Into the architecture layer, perspective into how to set the task assigned to each module, coordinate the most efficient operation, such as pipeline, distributed computing, parallel computing. At the logical level, consider how to implement one-step actions that will only make the required circuitry action. Circuit layer perspective is more refined, by adjusting the balance of signal arrival time, the size of the drive unit and other means to minimize the circuit's energy consumption. Here there is an important law, known as the rate of decline in efficiency:

Reducing power consumption at high levels of abstraction can be more efficient than low levels.

Therefore, to reduce power consumption is a systematic project that requires the joint efforts of software, hardware, circuit, technology and other personnel. Here, we will use the architectural and logical perspective for the following discussion.

  4.2 architecture considerations

1) Split working mode, the hardware can provide an interface, so that the software can control the circuit module action or not. Not working module hangs.

2) Distributed Computing: The entire task is divided into different modules, internally processed high activity signal. Although the total amount of calculation has not changed, but for a single module, the time required to reduce, you can down or step down.

3) Parallel calculation: the same amount of computation in the same time, but can be down / pressure. (The amount of calculation = the number of switches, the number of switches has not changed, but the cost of each switch power down)

4) pipeline: reduce the amount of computation per step, you can reduce the operating frequency in the case of the same performance.

5) Programmability vs. hard-wire tradeoff: The more programmability, the more power is needed to accomplish the same task.

 4.3 RAM power optimization

Obviously, large RAM consumes more power than small RAMs and splits the entire block of RAM into smaller blocks to reduce access to power.

It is noteworthy that most designers believe that the chip select signal is invalid, RAM into the minimum power consumption. In fact, if the data / address port signal is flipped this time, it will consume a considerable amount of power (about 20% of the active power). When not in use, the best way is to keep the chip select invalid, address, data is constant.

4.4 Clock Tree Unit / Connection

  4.4.1 clock gating principle

In a typical digital chip, clock network power consumption can account for 50% of the total, this is a huge number. An effective solution is to use clock gating to turn off the clock tree that currently does not work. For example, the following logic, EN is 0, the right side of the register bank clock can be turned off.

Clock gating logic to join the two ways: manual and automatic.

A) Manual mode

Join in each IP module's clock root node, EN signal can be set by the program.

B) Automatic mode

dc_shell> set_clock_gating_style (options) Select the method and conditions for clock gating

Dc_shell> analyze -f design.v Read in design

Dc_shell> elaborate MY_DESIGN Constructs a design

Dc_shell> insert_clock_gating will be eligible for logic gating

Dc_shell> create_clock -period 10 -name CLK Create the clock

Dc_shell> propagate_constraints -gate_clock Timing constraints for adding clock gating cells

The best combination of manual and automatic way to achieve the best efficiency.

In modern chip design, power consumption is drawing the designer's attention more and more. In this paper, we first analyze the components of power consumption, and then elaborate the power estimation method. Through the power estimation, designers can evaluate the efficiency of the design scheme in the early stage of the design in order to make the best choice. Finally, we focus on the analysis of power optimization methods, including architecture optimization, RAM power reduction, clock gating three techniques, and the introduction of the clock gating technology, a number of difficult problems one by one proposed solutions such as gating cell selection, timing Analysis, test support and more. Power analysis and optimization of the two complement each other, designers make good use of them to be more effective.